# Base name of the project file.
PROJECT=ss

# Part name
PART=xc3s1600efg320-4

# Implementation option file
# Pick one: fast_runtime balanced high_effort overnight weekend exhaustive
IMPLEMENT=fast_runtime

# Synthesis option file
SYNTH=xst_mixed

# Working directory name
WORK=work

.PHONY: all clean project

all:
	@mkdir -p $(WORK)
	xflow -wd $(WORK) -p $(PART) -synth $(SYNTH) -implement $(IMPLEMENT) -config bitgen $(PROJECT)

clean:
	rm -rf $(WORK)/

project:
	@rm -f $(PROJECT).prj
	@echo VHDL:
	@for i in $$(ls *.vhd 2> /dev/null); do echo "    " $$i; echo vhdl work $$i >> $(PROJECT).prj; done
	@echo Verilog:
	@for i in $$(ls *.v 2> /dev/null); do echo "    " $$i; echo verilog work $$i >> $(PROJECT).prj; done