Xilinx and Linux


Do I have to use that IDE if I'm just doing VHDL/Verilog?

Since the important parts of ISE WebPack are actually the command-line compiler tools, there is no need to use Xilinx's development environment if you can handle the build process. This is much more bulky than compiling software, and a lot of intermediate files are generated. To simplify the process, here is a template Makefile for compiling Verilog or VHDL source into bitstreams for Virtex and Spartan chips: Makefile

I've found that the IDE takes a lot of memory, and if you have less than 1GB then it's better to use only the command-line tools.

The downloader in ISE WebPack doesn't work.

Here's a simple command-line program that can download to Spartan II-series chips (I use it with the XC2S300E on the D2FT): xilinx_config

This program expects a DLC5-compatible programming cable (such as what comes with Digilent kits) to be accessible through /dev/parport0 (note that this is different from /dev/lp0). This requires that your kernel have the PPDEV driver installed. To turn on parallel port support with menuconfig, turn on these options:

  • Device Drivers -> Parallel port support -> Parallel port support
  • Device Drivers -> Parallel port support -> PC-style hardware
  • Device Drivers -> Character devices -> Support for user-space parallel port device drivers

The last option only appears when parallel port support is turned on. If you build this as a module, make sure it's loaded and that /dev/parport0 exists. Many distributions automatically create device nodes as necessary, but if yours doesn't, you can create it with:

mknod /dev/parport0 c 99 0

The program can easily be modified to use a different device.

xilinx_config takes only one command-line argument, the name of the bitstream to load. This must be a .bit file as produced by bitgen.

I have also used xc3sprog with a Digilent S3E-1600 board. It uses an inefficient protocol, but it works reliably. A problem to watch out for is that it always drives the JTAG lines, so you can't use the JTAG header for the FPGA after you load the new CPLD configuration.

What does Wind/U X-toolkit Error: wuDisplay: Can't open display mean?

(This doesn't happen on recent versions, but is kept here for reference.)

The IDE for ISE WebPack doesn't run out-of-the-box on many systems because it is built with a Windows-to-Unix toolkit that doesn't correctly parse the DISPLAY environment variable. To make it work, you have to remove the ".0". My DISPLAY variable is normally set to :0.0. To run the IDE, you need to do this:

DISPLAY=:0; ~/Xilinx/bin/lin/ise